Conventional approaches for interfacing a memory controller function with a double data rate (DDR) synchronous dynamic random access memory (SDRAM) use hard-coded intellectual property (IP) blocks for specific DDR SDRAM memory applications. For different data bus width applications, different physical interfaces are created. On the receive data path, the conventional approach is to perform a detailed SPICE (simulation program for integrated circuit emphasis) timing analysis and to carefully construct the read data path, such that the receive data can be re-synchronized to the memory controller function.
The conventional approaches do not have the flexibility to apply a particular physical interface IP for different DDR SDRAM memory bus configurations. The conventional approaches restrict the re-use of the physical interface IP in applications that have different system topologies. In addition, the conventional approaches build discrete low-level logic functions to handle the impedance update control of the IO buffers and one-quarter or one-fifth cycle delay tracking on the receive data path.
It would be desirable to have a configurable high-speed memory interface subsystem.